The present invention relates generally to electrical circuits, and more particularly to, an output buffer circuit for use in integrated circuits (ICs) that is compatible with many different supply voltages.
Current integrated circuits (ICs) that are used in modern electrical systems must be designed to effectively and efficiently communicate between many different types of devices that are powered by many different voltage supplies. For example, it is not unusual for a high voltage sensor or motor operating at tens or hundreds of volts to be wired for communication to a five volt line driver, a 3.3 volt microcontroller unit (MCU), a 2.5 volt timer peripheral, and/or a 1.8 volt memory device. In order for these devices to effectively communicate with each other in an electrical design, the input and output buffers of the various integrated circuits in the design must be able to accommodate many different voltages at any time and under any operating conditions. The need for voltage compatibility between many different power supply voltages used on many different ICs has significantly complicated the design of IC output buffers over recent years.
Due to the complexity required for wide-ranging voltage compatibility, output buffers are now consuming more IC substrate surface area, operating at relatively slower speeds due to added circuit overhead, and experiencing glitches or errors in operation that have rendered some output buffers less flexible or nonfunctional in some applications or uses.
The above issues can be illustrated with respect to FIG. 1. FIG. 1 illustrates a conventional output buffer circuit 10 that is currently used in the IC industry. The circuit 10 is provided with a data output (DO) signal 13 and an output enable (OE) 15 as shown in FIG. 1. A driver control circuit 11 is used to adjust voltages up or down to more compatible voltages for circuit 10, and is used to convert the DO and OE signals to control signals that can be used by a P channel pull-up portion of the circuit 10. An N channel pre-driver 14 performs similar functions for N channel devices and various pull-down circuitry illustrated in circuit 10.
For the P channel pull-up circuitry of FIG. 1, the driver control circuit 11 will provide a control signal, responsive to the OE and DO signals, to one or more inverters 12. The inverter 12 will provide, via interconnection 17, a drive high signal to a switch 16. When the signal 17 is a logic zero, the circuit 10 is to drive an output pad 28 to a logic one, when the signal 17 is logic one, the P channel pull-up circuitry is disabled, whereby the circuit 10 is either in a tri-state mode or a pull-down mode. The switch 16 contains an N channel transistor that has a gate electrode connected to the power supply voltage (VDD). The switch 16 also contains a P channel pass transistor that is gated by a voltage resident on the output pad 28.
The switch 16 will pass the voltage resident on node 17 to the node 19. The node 19 provides this signal to a pull-up P channel transistor 18. The pull-up transistor 18 is coupled to VDD and is selectively enabled by the node 19 to pull the output pad 28 to a high voltage when the output pad 28 is to be driven to a logic one. The N channel pull-down transistor 20 illustrated in FIG. 1 is selectively enabled, mutually exclusive of the transistor 18, to selectively pull the output pad 28 to a low voltage to output a logic zero value. A P channel transistor 22 is used to render the output buffer of FIG. 1 compatible with other voltages that may be provided from time to time on output pad 28 by other circuitry. For example, voltages higher than VDD may be applied to the pad 28, whereby the transistor 22 ensures that the voltage at the node 19 follows the voltage at the output pad 28. Such voltage following in pad overvoltage cases is desired so that the transistor 18 does not erroneously turn on during overvoltage events whereby IC power is wasted.
A switch 24 in FIG. 1 is also used to provide some voltage compatibility to the circuit 10 of FIG. 1. Switch 24 selectively biases the bulk connections of transistors 18 and 22 and a bulk connection of the P channel transistor of switch 16 to avoid adverse consequences of voltage mismatches between VDD and the pad voltage on pad 28. Generally, the switch 24 provides a greater of either VDD or a voltage on the output pad 28 to the bulks of the various bulk-interconnected P channel transistors in FIG. 1 to ensure that high voltages provided on the pad 28 do not adversely affect the lower voltage output buffer circuit 10. Therefore, several devices or protection mechanisms in FIG. 1 have already been added to the surface area of the output buffer circuit to ensure that the output pad 28 is somewhat compatible with other supply voltages.
However, it has been found that erroneous operation can result using the circuit of FIG. 1, even though precautions have been taken to add circuitry to ensure that circuit 10 of FIG. 1 is compatible with other power supply voltage levels. In common integrated circuit designs, some output pads 28 may be used as an input mechanism during reset operations. In other words, during reset, the output pins 28 provide binary values into the packaged IC in order to allow a microprocessor, microcontroller, DSP, or like device within the IC to be configured dynamically upon reset. For example, the pad 28 of FIG. 1 is illustrated as being connected to a pull-down resistor 26. Upon reset, the resistor 26 is designed to pull the pad 28 to a ground potential while the transistors 18 and 20 are shut off in reset to tri-state the circuit 10 from the pad 28. The IC that includes the circuit 10 can then read the voltage value on the pad 28 and configure itself accordingly. When a pull-down resistor 26 is used, the device is to configure itself into a first mode of operation in response to the logic zero on the pad 28. Had the pad 28 been connected to a pull up resistor which drove the pad 28 to a logic one, the IC would have programmed itself into a different mode of operation.
In FIG. 1, experiments have shown that the pad 28 has in some cases been driven by the circuit 10 to a logic one value or 3.3 volts followed by a reset event. At that point, with the pad at 3.3 volts, OE 15 will turn off the transistors 18 and 20 and cause circuit 10 to enter a tri-state mode. In this tri-state mode, the node 19 is driven to a logic one in order to shut the transistor 18 off. However, the 3.3 volts provided at node 17 will experience an N channel threshold voltage drop (Vtn) through the switch 16 whereby the voltage at node 19 will be VDD minus one Vtn. If Vtn is greater than the threshold voltage of the transistor 18 (Vtp), then the transistor 18 may be operating at an on-state or a partially on-state. When on or partially on, the transistor 18 is supplying some leakage current to the pad 28 whereby the path from VDD through the transistor 18 and resistor 26 to ground begins to function as a voltage divider. Depending upon the strengths of the devices 18 and 26, it has been found that the resister 26 is not always strong enough to pull the pad 28 to ground as was intended during reset. Due to this inability of the resistor 26 to pull the pad 28 to ground, the IC which uses the circuit of FIG. 10 to configure itself on reset will be configured into a wrong operational state (i.e., it will sense a logic one on the pad 28 when a logic zero was intended).
In addition to the above problem of erroneous configuration operations, the DO and OE signals are generally provided from a central processing unit (CPU) core or microcontroller that is operating in low voltage modes in the vicinity of 1.8 volts to 2.5 volts. In the case where the VDD of FIG. 1 is higher than that voltage provided on CPU signals (i.e., the circuit 10 may be using VDD values of 3.3 volts or 5 volts), the driver control circuitry 11 must level shift the DO and/or OE voltages from the lower voltage to a higher voltage that is more compatible with the higher voltage VDD. Such level shifting operations have been shown to take several nanoseconds of time in some designs. This level shifting delay of several nanoseconds impacts the ability of a driver to provide output data in a timely manner. Therefore, in addition to the need to correct the operational errors experienced by existing output buffers, a need exists in the industry to improve the performance and response time of output buffers while simultaneously ensuring that voltage compatibility is still adequate.
Therefore, a need exists in the industry for an output buffer that provides error free operation over wide voltage ranges while improving the DO-to-pad propagation delay of the output buffer and/or reducing a surface area consumed by the output buffer circuitry.